DSP56300FM中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

Features

DSP56300 Modular Chassis

? 120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V.

? Object Code Compatible with the 56K core.

? Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic

support.

? Program Control with position independent code support and instruction cache support.

? Six-channel DMA controller.

? PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors

(1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise.

? Internal address tracing support and OnCE? for Hardware/Software debugging.

? JTAG port.

? Very low-power CMOS design, fully static design with operating frequencies down to DC.

? STOP and WAIT low-power standby modes.

On-chip Memory Configuration

? 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.

? 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

? 40Kx24 Bit Program ROM.

? 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as

Instruction Cache or for Program ROM patching.

? 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM

resulting in up to 10Kx24 Bit of Program RAM.

Off-chip Memory Expansion

? External Memory Expansion Port.

? Off-chip expansion up to two 16M x 24-bit word of Data memory.

? Off-chip expansion up to 16M x 24-bit word of Program memory.

? Simultaneous glueless interface to SRAM and DRAM.

Peripheral Modules

? Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony,

AC97, network and other programmable protocols.

? Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S,

Sony, AC97, network and other programmable protocols

The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and

HCKT (high frequency clocks)

? Serial Host Interface (SHI): SPI and I2C protocols, multi master capability, 10-word receive FIFO,

support for 8, 16 and 24-bit words.

? Byte-wide parallel Host Interface (HDI08) with DMA support.

? Triple Timer module (TEC).

? Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958,

CP-340 and AES/EBU digital audio formats.

? Pins of unused peripherals (except SHI) may be programmed as GPIO lines.