EDE1108AJBG-8E-F中文資料美光科技數(shù)據(jù)手冊PDF規(guī)格書

EDE1108AJBG (128M words ×8 bits)

EDE1116AJBG (64M words ×16 bits)

Features

? Double-data-rate architecture; two data transfers per clock cycle

? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture

? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

? DQS is edge-aligned with data for READs; center aligned with data for WRITEs

? Differential clock inputs (CK and /CK)

? DLL aligns DQ and DQS transitions with CK transitions

? Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

? Data mask (DM) for write data

? Posted /CAS by programmable additive latency for better command and data bus efficiency

? Programmable RDQS, /RDQS output for making ×8 organization compatible to ×4 organization

? /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation

? Off-Chip Driver (OCD) impedance adjustment is not supported.