EDE5104GBSA-5A-E中文資料美光科技數(shù)據(jù)手冊PDF規(guī)格書

Description

The EDE5104GB is a 512M bits DDR-II SDRAM organized as 33,554,432 words × 4 bits × 4 banks.

The EDE5108GB is a 512M bits DDR-II SDRAM organized as 16,777,216 words × 8 bits × 4 banks. It packaged in 64-ball μBGA? package.

Features

? 1.8V power supply

? Double-data-rate architecture: two data transfers per clock cycle

? Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver

? DQS is edge aligned with data for READs: centeraligned with data for WRITEs

? Differential clock inputs (CK and /CK)

? DLL aligns DQ and DQS transitions with CK transitions

? Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS

? Four internal banks for concurrent operation

? Data mask (DM) for write data

? Burst lengths: 4, 8

? /CAS Latency (CL): 3, 4, 5

? Auto precharge operation for each burst access

? Auto refresh and self refresh modes

? 7.8μs average periodic refresh interval

? 1.8V (SSTL_18 compatible) I/O

? Posted CAS by programmable additive latency for better command and data bus efficiency

? Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality

? Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization

? /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation.

? μBGA package is lead free solder (Sn-Ag-Cu)