首頁(yè)>GS8161E18BD-200I>規(guī)格書(shū)詳情
GS8161E18BD-200I中文資料GSI數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
GS8161E18BD-200I |
| 功能描述 | 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs |
| 文件大小 |
1.39199 Mbytes |
| 頁(yè)面數(shù)量 |
35 頁(yè) |
| 生產(chǎn)廠商 | GSI Technology |
| 企業(yè)簡(jiǎn)稱 |
GSI |
| 中文名稱 | GSI Technology官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-2-23 15:00:00 |
| 人工找貨 | GS8161E18BD-200I價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
GS8161E18BD-200I規(guī)格書(shū)詳情
Functional Description
Applications
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Features
? FT pin for user-configurable flow through or pipeline operation
? Dual Cycle Deselect (DCD) operation
? IEEE 1149.1 JTAG-compatible Boundary Scan
? 2.5 V or 3.3 V +10/–10 core power supply
? 2.5 V or 3.3 V I/O supply
? LBO pin for Linear or Interleaved Burst mode
? Internal input resistors on mode pins allow floating mode pins
? Default to Interleaved Pipeline mode
? Byte Write (BW) and/or Global Write (GW) operation
? Internal self-timed write cycle
? Automatic power-down for portable applications
? JEDEC-standard 100-lead TQFP package
? RoHS-compliant 100-lead TQFP and 165-bump BGA packages available
產(chǎn)品屬性
- 型號(hào)：
GS8161E18BD-200I
- 制造商：
GSI
- 制造商全稱：
GSI Technology
- 功能描述：
1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
GSI Technology |
2022+ |
原廠原包裝 |
8600 |
全新原裝 支持表配單 中國(guó)著名電子元器件獨(dú)立分銷 |
詢價(jià) |
