HCS161DMSR中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The Intersil HCS161MS is a Radiation Hardened 4-Input Binary; synchronous counter featuring asynchronous reset and lookahead carry logic. The HCS161 has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (p0 - p3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCS161MS has two count output, IC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count.

Features

? 3 Micron Radiation Hardened SOS CMOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse

? Cosmic Ray Upset Immunity 2 x 10-9 Error/Bit Day (Typ)

? Latch-Up Free Under Any Conditions

? Military Temperature Range: -55°C to +125°C

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 0.3 VCC Max

??? - VIH = 0.7 VCC Min

? Input Current Levels Ii ≤ 5μA at VOL, VOH