HD64F2633F25中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Overview

The H8S/2633 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas’ proprietary architecture, and equipped with peripheral functions on-chip.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include DMA controller (DMAC)*2, data transfer controller (DTC)*2 bus masters, ROM and RAM memory, a 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG)*2, 8-bit timer*2, 14-bit PWM timer (PWM)*2, watchdog timer (WDT), serial communication interface (SCI, IrDA*2), A/D converter, D/A converter*2, and I/O ports. It is also possible to incorporate an on-chip PC bus interface (IIC)*2 as an option.

On-chip ROM is available as 256-kbyte flash memory (F-ZTAT? version)*1 or as 256-, 128-, or 64-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode.

The features of the H8S/2633 Group are shown in table 1.1.