首頁>HD74CDC2510BTEL>規(guī)格書詳情
HD74CDC2510BTEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書
HD74CDC2510BTEL規(guī)格書詳情
Description
The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2510B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.
Features
? Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
? Phase-lock loop clock distribution for synchronous DRAM applications
? External feedback (FBIN) pin is used to synchronize the outputs to the clock input
? No external RC network required
? Support spread spectrum clock (SSC) synthesizers
產(chǎn)品屬性
- 型號(hào)：
HD74CDC2510BTEL
- 制造商：
Renesas Electronics Corporation
- 功能描述：
FACT - Tape and Reel
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
HIT |
9906+ |
SSOP24 |
304 |
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價(jià) | ||
RENESAS |
23+ |
TSSOP24 |
2304 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
HD |
24+ |
TSSOP-24 |
35200 |
一級(jí)代理/放心采購 |
詢價(jià) | ||
RENESAS |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量 |
詢價(jià) | ||||
HIT |
24+ |
TSSOP24 |
100 |
詢價(jià) | |||
HAT |
1822+ |
TSSOP24 |
9852 |
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn)!! |
詢價(jià) | ||
HIT |
23+ |
SOP.16 |
5000 |
原裝正品,假一罰十 |
詢價(jià) | ||
HITACHI/日立 |
22+ |
TSSOP24L |
14008 |
原裝正品 |
詢價(jià) | ||
HITACHI |
2023+ |
SSOP-24 |
50000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
HIT |
1999 |
5483 |
原裝正品現(xiàn)貨庫存價(jià)優(yōu) |
詢價(jià) |
