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HD74LV373AFPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

HD74LV373AFPEL
廠商型號(hào)

HD74LV373AFPEL

功能描述

Octal D-type Transparent Latches with 3-state Outputs

文件大小

86.37 Kbytes

頁(yè)面數(shù)量

11 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-2-15 1:36:00

HD74LV373AFPEL規(guī)格書詳情

Description

The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.

Features

? VCC = 2.0 V to 5.5 V operation

? All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

? All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

? Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

? Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

? Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)

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20+
SOP20
2960
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RENESAS
2020+
SOP5.2
80000
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HITACHI/日立
23+
NA/
7250
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HIT
24+
SOP20
20000
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RENESAS
24+
SOP
2987
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HIT
21+
SOP
4000
原裝現(xiàn)貨假一賠十
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22+
5000
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HIT
23+
SSOP
28000
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HIT
24+
65300
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RENESAS/PB
589220
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