HEF40194BN中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), and four buffered parallel outputs (O0 to O3). When LOW, MR resets all stages and forces O0 to O3 LOW, overriding all other input conditions. When MR is HIGH, the operation mode is controlled by S0 and S1 as shown in the function table.

Serial and parallel operation are edge-triggered on the LOW to HIGH transition of CP. The inputs at which the data are to be entered and S0, S1 must be stable for a set-up time before the LOW to HIGH transition of CP.