HEF4040BT集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

1. General description

The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter

advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Inputs

are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting

applications.

2. Features and benefits

? Wide supply voltage range from 3.0 V to 15.0 V

? CMOS low power dissipation

? High noise immunity

? Tolerant of slow clock rise and fall time

? Fully static operation

? 5 V, 10 V, and 15 V parametric ratings

? Standardized symmetrical output characteristics

? Complies with JEDEC standard JESD 13-B

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? Specified from -40 °C to +85 °C

3. Applications

? Frequency dividing circuits

? Time delay circuits

? Control counters