HEF4520B集成電路（IC）的計數(shù)器除法器規(guī)格書PDF中文資料

1. General description

The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0

and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master

reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1

is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be

used as the clock input to the counter and the other clock input may be used as a clock enable

input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1.

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

voltages in excess of VDD.

2. Features and benefits

? Tolerant of slow clock rise and fall times

? Fully static operation

? 5 V, 10 V, and 15 V parametric ratings

? Wide supply voltage range from 3.0 V to 15.0 V

? CMOS low power dissipation

? High noise immunity

? Standardized symmetrical output characteristics

? Complies with JEDEC standard JESD 13-B

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? Specified from -40 °C to +85 °C