HI3197JCQ中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書

10-Bit, 125 MSPS D/A Converter

The HI3197 is a high-speed D/A converter which can perform the multiplexed input of the two system 10-bit data. The maximum conversion rate achieves 125 MSPS. The multiplexed operation is possible by the 1/2 frequency divided clock or by halving the frequency of the clock with the clock frequency divider circuit having the reset pin in the IC. The data input is TTL; the clock input pin and reset input pin can select either TTL or PECL according to the application.

Features

? Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits

? Conversion Rate 125 MSPS (PECL) 100 MSPS (TTL)

? Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL

? Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)

? Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV?s

? Clock, Reset Input Level: TTL and PECL Compatible 2:1 Multiplexed Input Function

? 1/2 Frequency-Divided Clock Output Possible by the BuiltIn Clock Frequency Divider Circuit

? Voltage Output (50? Load Drive Possible)

? Single Power Supply or ±Dual Power Supplies

? Polarity Switching Function of Reset Signal

Applications

? LCD

? DDS

? HDTV

? Communications (QPSK, QAM)