HM62W16255HLJP-15中文資料日立數(shù)據(jù)手冊PDF規(guī)格書

Description

The HM62W16255H is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255H is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.

Features

? Single 3.3 V supply: 3.3 V ± 0.3V

? Access time: 12/15 ns (max)

? Completely static memory

- No clock or timing strobe required

? Equal access and cycle times

? Directly TTL compatible

- All inputs and outputs

? Operating current: 180/160 mA (max)

? TTL standby current: 60/50 mA (max)

? CMOS standby current: 5 mA (max)

: 1mA (max) (L-version)

? Data retension current: 0.6 mA (max) (L-version)

? Data retension voltage: 2.0 V (min) (L-version)

? Center VCC and VSS type pinout