HS-81C55RH中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened Self Aligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices.

Features

? Electrically Screened to SMD # 5962-96766

? QML Qualified per MIL-PRF-38535 Requirements

? Radiation Hardened EPI-CMOS

- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)

- Transient Upset. . . . . . . . . . . . . . . . . .>1 x 108 rad(Si)/s

- Latch-Up Free. . . . . . . . . . . . . . . . . .>1 x 1012 rad(Si)/s

? Electrically Equivalent to Sandia SA 3001

? Pin Compatible with Intel 8155/56

? Bus Compatible with HS-80C85RH

? Single 5V Power Supply

? Low Standby Current . . . . . . . . . . . . . . . . . . . .200μA Max

? Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz

? Completely Static Design

? Internal Address Latches

? Two Programmable 8-Bit I/O Ports

? One Programmable 6-Bit I/O Port

? Programmable 14-Bit Binary Counter/Timer

? Multiplexed Address and Data Bus

? Self Aligned Junction Isolated (SAJI) Process

? Military Temperature Range . . . . . . . . . . . -55℃ to 125℃