HY27UG088GDM中文資料海力士數(shù)據(jù)手冊(cè)PDF規(guī)格書

SUMMARY DESCRIPTION

The HYNIX HY27UG088G(5/D)M series is a 1Gx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.

The device contains 8192 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells.

A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif ferent densities, without any rearrangement of footprint.

The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Read ID2 extension.

The HYNIX HY27UG088G(5/D)M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

- Cost effective solutions for mass storage applications

NAND INTERFACE

- x8 width.

- Multiplexed Address/ Data

- Pinout compatibility for all densities

SUPPLY VOLTAGE

- 3.3V device: VCC = 2.7 to 3.6V : HY27UG088G(5/D)M

Memory Cell Array

= (2K+ 64) Bytes x 64 Pages x 8,192 Blocks

PAGE SIZE

- x8 device : (2K + 64 spare) Bytes

: HY27UG088G(5/D)M

BLOCK SIZE

- x8 device: (128K + 4K spare) Bytes

PAGE READ / PROGRAM

- Random access: 25us (max.)

- Sequential access: 30ns (min.)

- Page program time: 200us (typ.)

COPY BACK PROGRAM MODE

- Fast page copy without external buffering

CACHE PROGRAM MODE

- Internal Cache Register to improve the program throughput

FAST BLOCK ERASE

- Block erase time: 2ms (Typ.)

STATUS REGISTER

ELECTRONIC SIGNATURE

- 1st cycle: Manufacturer Code

- 2nd cycle: Device Code

CHIP ENABLE DONT CARE

- Simple interface with microcontroller

SERIAL NUMBER OPTION

HARDWARE DATA PROTECTION

- Program/Erase locked during Power transitions

DATA INTEGRITY

- 100,000 Program/Erase cycles (with 1bit/512byte ECC)

- 10 years Data Retention

PACKAGE

- HY27UG088G5M-T(P)

: 48-Pin TSOP1 (12 x 20 x 1.2 mm)

- HY27UG088G5M-T (Lead)

- HY27UG088G5M-TP (Lead Free)

- HY27UG088GDM-UP

:52- ULGA (12 x 17 x 0.65 mm)

- HY27UG088GDM-DP (Lead Free)