HYB3164800AT-50中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in an advanced second generation 64Mbit 0,35 μm CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800AJ/AT to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package.

Advanced Information

? 8 388 608 words by 8-bit organization

? 0 to 70 °C operating temperature

? Fast Page Mode operation

? Single + 3.3 V (± 0.3V) power supply

? Low power dissipation:

max. 396 mW active ( HYB 3164800AJ/AT(L) -40)

max. 324 mW active ( HYB 3164800AJ/AT(L) -50)

max. 270 mW active ( HYB 3164800AJ/AT(L) -60)

max. 558 mW active ( HYB 3165800AJ/AT(L) -40)

max. 468 mW active ( HYB 3165800AJ/AT(L) -50)

max. 378 mW active ( HYB 3165800AJ/AT(L) -60)

7.2 mW standby (LVTTL)

3.24 mW standby (LVCMOS)

720 μW standby for L-versions

? Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only)

? 8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800AJ/AT) 4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800AJ/AT)

? 256 msec refresh period for L-versions

? Plastic Package: P-SOJ-32-1 400 mil HYB 3164(5)800AJ P-TSOPII-32-1 400 mil HYB 3164(5)800AT(L)