HYB39S64800BT-8中文資料英飛凌數(shù)據手冊PDF規(guī)格書

The HYB 39S64400/800/160BT are four bank Synchronous DRAM’s organized as 4 banks × 4MBit ×4, 4 banks × 2 MBit ×8 and 4 banks × 1 Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefects multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using the Infineon advanced 0.2 μm 64 MBit DRAM process technology.

? Fully Synchronous to Positive Clock Edge

? 0 to 70 °C operating temperature

? Four Banks controlled by BA0 & BA1

? Programmable CAS Latency: 2, 3

? Programmable Wrap Sequence: Sequential or Interleave

? Programmable Burst Length: 1, 2, 4, 8

? Full page (optional) for sequential wrap around

? Multiple Burst Read with Single Write Operation

? Automatic and Controlled Precharge Command

? Data Mask for Read/Write Control (x4, x8)

? Data Mask for Byte Control (x16)

? Auto Refresh (CBR) and Self Refresh

? Suspend Mode and Power Down Mode

? 4096 Refresh Cycles / 64 ms

? Random Column Address every CLK (1-N Rule)

? Single 3.3 V ± 0.3 V Power Supply

? LVTTL Interface

? Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16)

? -7.5 version for PC133 3-3-3 application

-8 version for PC100 2-2-2 applications