I.MX8XLITE中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

Introduction

This data sheet contains specifications for the i.MX 8XLite

processors. The devices have advanced multicore processing

with V2X acceleration supported by Arm? cores. Memory

interfaces for this device include:

? LPDDR4

? DDR3L

? 2× Quad SPI or 1× Octal SPI (FlexSPI)

? eMMC 5.1, RAW NAND, and SD 3.0

Feature

-I/O

1× PCIe 3.0 (1-lane) with L1 substate support. PCIe 1.0 and 2.0 compliant. PCIe 3.0

capable, contact your NXP representative.

2× USB 2.0 ports

1× 1Gb Ethernet with AVB

1x 1Gb Ethernet with TSN

3× CAN/CAN-FD

6× UARTs:

? 4× UARTs (3× with hardware flow control)

? 1× UART tightly coupled with Cortex-M4F cores

? 1× SCU UART (Note: SCU UART is dedicated to the SCU and not available for

general use)

6× I2C

? 4× I2C: High Speed, DMA support

? 1× I2C: PMIC control (SCU, dedicated)

? 1× I2C: Cortex M4F (dedicated)

4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only)

1× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly

connected to this module)

1× SPDIF (Tx and Rx)

1× 6-channel ADC converter

3.3 V/1.8 V GPIO

4× PWM channels

4× LPSPI

-Packaging

Case FCPBGA 15 x 15 mm, 0.56 and 0.8 mm mixed pitch