ICS670-03中文資料ICST數(shù)據(jù)手冊PDF規(guī)格書

Description

The ICS670-03 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. It is identical to the ICS670-01, but with an increased maximum output frequency of 210 MHz. Part of ICS’ ClockBlocksTM family, the part’s zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin.

Features

? Packaged in 16-pin SOIC

? Available in Pb (lead) free package

? Clock inputs from 5 to 210 MHz (see page 2)

? Patented PLL with low phase noise

? Output clocks up to 210 MHz at 3.3V

? 15 selectable on-chip multipliers

? Power down mode available

? Low phase noise: -124 dBc/Hz at 10 kHz

? Output enable function tri-states outputs

? Low jitter 15 ps one sigma

? Advanced, low power, sub-micron CMOS process

? Industrial temperature rated

? Operating voltage of 3.3 V or 5 V