ICS8745BI中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? Five differential LVDS outputs designed to meet

or exceed the requirements of ANSI TIA/EIA-644

? Selectable differential clock inputs

? CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

? Output frequency range: 31.25MHz to 700MHz

? Input frequency range: 31.25MHz to 700MHz

? VCO range: 250MHz to 700MHz

? External feedback for “zero delay” clock regeneration

with configurable frequencies

? Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

? Cycle-to-cycle jitter: 30ps (maximum)

? Output skew: 40ps (maximum)

? Static phase offset: 25ps ± 125ps

? Full 3.3V supply voltage

? -40°C to 85°C ambient operating temperature

? Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages