IO15RSB0中文資料美高森美數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
IO15RSB0 |
| 功能描述 | ProASIC3 Flash Family FPGAs with Optional Soft ARM Support |
| 文件大小 |
9.57546 Mbytes |
| 頁面數(shù)量 |
210 頁 |
| 生產(chǎn)廠商 | Microsemi Corporation |
| 企業(yè)簡稱 |
Microsemi【美高森美】 |
| 中文名稱 | 美高森美公司官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-5-23 23:01:00 |
| 人工找貨 | IO15RSB0價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
IO15RSB0規(guī)格書詳情
Features and Benefits
High Capacity
? 15 k to 1 M System Gates
? Up to 144 kbits of True Dual-Port SRAM
? Up to 300 User I/Os
Reprogrammable Flash Technology
? 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
? Instant On Level 0 Support
? Single-Chip Solution
? Retains Programmed Design when Powered Off
High Performance
? 350 MHz System Performance
? 3.3 V, 66 MHz 64-Bit PCI?
In-System Programming (ISP) and Security
? ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM?-enabled ProASIC?3 devices) via JTAG (IEEE 1532–compliant)?
? FlashLock? to Secure FPGA Contents
Low Power
? Core Voltage for Low Power
? Support for 1.5 V-Only Systems
? Low-Impedance Flash Switches
High-Performance Routing Hierarchy
? Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
? 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
? 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
? Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
? Bank-Selectable I/O Voltages—up to 4 Banks per Chip
? Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X? and LVCMOS 2.5 V / 5.0 V Input
? Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
? I/O Registers on Input, Output, and Enable Paths
? Hot-Swappable and Cold Sparing I/Os?
? Programmable Output Slew Rate? and Drive Strength
? Weak Pull-Up/-Down
? IEEE 1149.1 (JTAG) Boundary Scan Test
? Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL?
? Six CCC Blocks, One with an Integrated PLL
? Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
? Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory?
? 1 kbit of FlashROM User Nonvolatile Memory
? SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)?
? True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
? M1 ProASIC3 Devices—ARM?Cortex?-M1 Soft Processor Available with or without Debug
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
ENE |
24+ |
NA/ |
4264 |
原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開票 |
詢價(jià) | ||
TOSH |
23+ |
QFP48 |
20000 |
全新原裝假一賠十 |
詢價(jià) | ||
TOSH |
04+ |
QFP48 |
47 |
全新原裝進(jìn)口自己庫存優(yōu)勢(shì) |
詢價(jià) | ||
ENE |
1741+ |
LQFP |
6528 |
只做進(jìn)口原裝正品假一賠十! |
詢價(jià) | ||
ENE |
23+ |
QFP |
15000 |
一級(jí)代理原裝現(xiàn)貨 |
詢價(jià) | ||
ENE |
22+ |
TQFP |
12245 |
現(xiàn)貨,原廠原裝假一罰十! |
詢價(jià) | ||
ENE |
2402+ |
QFP |
8324 |
原裝正品!實(shí)單價(jià)優(yōu)! |
詢價(jià) | ||
新 |
14 |
全新原裝 貨期兩周 |
詢價(jià) | ||||
ENE |
24+ |
TQFP |
39197 |
鄭重承諾只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) | ||
原裝IC |
QFN |
15620 |
一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢(shì)長期供貨 |
詢價(jià) |
