K4T51043QC-ZCCC中文資料三星數(shù)據(jù)手冊PDF規(guī)格書

The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4 banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed double data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications.

The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination

Key Features

? JEDEC standard 1.8V ± 0.1V Power Supply

? VDDQ = 1.8V ± 0.1V

? 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin

? 4 Banks

? Posted CAS

? Programmable CAS Latency: 3, 4, 5

? Programmable Additive Latency: 0, 1 , 2 , 3 and 4

? Write Latency(WL) = Read Latency(RL) -1

? Burst Length: 4 , 8(Interleave/nibble sequential)

? Programmable Sequential / Interleave Burst Mode

? Bi-directional Differential Data-Strobe (Single-ended data strobe is an optional feature)

? Off-Chip Driver(OCD) Impedance Adjustment

? On Die Termination

? Special Function Support

-PASR(Partial Array Self Refresh)

-50ohm ODT

-High Temperature Self-Refresh rate enable

? Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < T CASE < 95 °C

? All of Lead-free products are compliant for RoHS