KBY00U00VA-B450中文資料三星數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The KBY00U00VA is a Multi Chip Package Memory which combines 8Gbit DDP Nand Flash Memory(organized with two pieces of 4Gbit Nand Flash Memory) and 4Gbit DDR synchronous high data rate Dynamic RAM(organized with two pieces of 2Gbit Mobile DDR SDRAM).

NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 420μs(TBD) on the (2K+64)Word page and an erase operation can be performed in typical 3ms(TBD) on a (128K+4K)Word block. Data in the data register can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write intensive systems can take advantage of the device′s extended reliability of TBD program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

In 4G bit DDP Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES

? Operating Temperature : -25°C ~ 85°C

? Package : 137 FBGA Type - 10.5mmx13mmx1.2mmt, 0.8mm pitch

? Voltage Supply

- 1.8V Device : 1.7V ~ 1.95V

? Organization

- Memory Cell Array :

(256M + 8M) x 16bit for 4Gb

(512M + 16M) x 16bit for 8Gb DDP

- Data Register : (2K + 64) x 16bit

? Automatic Program and Erase

- Page Program : (2K + 64)Word

- Block Erase : (128K + 4K)Word

? Page Read Operation

- Page Size : (2K + 64)Word

- Random Read : 60μs(Max.) (TBD)

- Serial Access : 42ns(Min.)

? Fast Write Cycle Time

- Page Program time : 420μs(Typ.) (TBD)

- Block Erase Time : 3ms(Typ.) (TBD)

? Command/Address/Data Multiplexed I/O Port

? Hardware Data Protection

- Program/Erase Lockout During Power Transitions

? Reliable CMOS Floating-Gate Technology

-Endurance : TBD Program/Erase Cycles with 4bit/256Word ECC for x16

? Command Driven Operation

? Unique ID for Copyright Protection

? VDD/VDDQ = 1.8V/1.8V

? Double-data-rate architecture; two data transfers per clock cycle.

? Bidirectional data strobe (DQS).

? Four banks operation.

? Differential clock inputs (CK and CK).

? MRS cycle with address key programs.

- CAS Latency (3)

- Burst Length (2, 4, 8, 16)

- Burst Type (Sequential & Interleave)

? EMRS cycle with address key programs.

- Partial Array Self Refresh (Full, 1/2, 1/4 Array)

- Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8)

? Internal Temperature Compensated Self Refresh.

? All inputs except data & DM are sampled at the positive going edge of the system clock (CK).

? Data I/O transactions on both edges of data strobe, DM for masking.

? Edge aligned data output, center aligned data input.

? No DLL; CK to DQS is not synchronized.

? DM for write masking only.

? Auto refresh duty cycle.

- 7.8us

? Clock stop capability

? 2/CS, 2CKE