LAN83C180中文資料SMSC數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The LAN83C180 is a single chip CMOS physical layer (PHY) solution providing all necessary functions between the Media Independent Interface (MII) and the magnetics connected to Category 5 twisted pair media. It is designed for 10BASE-T and 100BASE-TX Ethernet, and is based on the IEEE 802.3 specifications.

FEATURES

? Single Chip 100Base-TX/10Base-T Ethernet Physical Layer (PHY) Solution

? Dual Speed – 10/100 Mbps

? Full MII Interface for a Glueless MAC Connection

? MI Interface for Configuration and Status

? Half Duplex and Full Duplex in Both 10BASE-T and 100BASE-TX

? Repeater Mode

? Extended Register Set

? Integrated 10BASE-T Transceivers and Receive/Transmit Filters

? Integrated Adaptive Equalizer and Base Line Wander Correction

? Full Auto Negotiation Support for 10BASE-T and 100BASE-TX Both Half and Full Duplex

? Parallel Detection for Supporting Non Auto Negotiation Legacy in Link Partners

? Low Current

? Low Power Mode

? Internal Power on Reset

? Single Magnetics for 10BASE-T and 100BASE-TX Operation for a Single RJ45 Connector

? Support for IEEE-802.3x Flow Control Specification

? 5 Integrated Status LED Drivers

- Full Duplex

- 10/100

- Activity

- Collision

- Link

? Low External Component Count

? 64 Pin TQFP Package (1.0 mm Body Thickness)