LH28F400SUT-NC60中文資料夏普微數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The LH28F400SU-NC is a high performance 4M (4,194,304) block erasable non-volatile random access memory organized as either 256K × 16 or 512K × 8. The LH28F400SU-NC includes thirty-two 16K (16,384) blocks. A chip memory map is shown in Figure 5.

The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use.

Among the significant enhancements of the LH28F400SU-NC:

? 5 V Read, Write/Erase Operation (5 V VCC, VPP)

? Low Power Capability

? Improved Write Performance

? Dedicated Block Write/Erase Protection

? Command-Controlled Memory Protection Set/Reset Capability

FEATURES

? User-Configurable x8 or x16 Operation

? 5 V Write/Erase Operation (5 V VPP)

– No Requirement for DC/DC Converter to Write/Erase

? 60 ns Maximum Access Time

(VCC = 5.0 V ± 0.25 V)

? 80ns Maximum Access Time

(VCC = 5.0 V ± 0.5 V)

? 32 Independently Lockable Blocks (16K)

? 100,000 Erase Cycles per Block

? Automated Byte Write/Block Erase

– Command User Interface

– Status Register

– RY?/BY? Status Output

? System Performance Enhancement

– Erase Suspend for Read

– Two-Byte Write

– Full Chip Erase

? Data Protection

– Hardware Erase/Write Lockout during Power Transitions

– Software Erase/Write Lockout

? Independently Lockable for Write/Erase

on Each Block (Lock Block and Protect Set/Reset)

? 5 μA (Typ.) ICC in CMOS Standby

? 0.2 μA (Typ.) Deep Power-Down

? State-of-the-Art 0.45 μm ETOX? Flash Technology

? 56-Pin, 1.2 mm × 14 mm × 20 mm TSOP (Type I) Package

? 48-Pin, 1.2 mm × 12 mm × 18 mm TSOP (Type I) Package

? 44-Pin, 600-mil SOP Package