M470L3223DT0-CLB0中文資料三星數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The Samsung M470L3223DT0 is 32M bit x 64 Double Data Rate SDRAM high density memory modules based on third gen of 256Mb DDR SDRAM respectively.

The Samsung M470L3223DT0 consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM.

FEATURE

? Performance range

? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

? Double-data-rate architecture; two data transfers per clock cycle

? Bidirectional data strobe(DQS)

? Differential clock inputs(CK and CK)

? DLL aligns DQ and DQS transition with CK transition

? Programmable Read latency 2, 2.5 (clock)

? Programmable Burst length (2, 4, 8)

? Programmable Burst type (sequential & interleave)

? Edge aligned data output, center aligned data input

? Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

? Serial presence detect with EEPROM

? PCB :Height 1250 (mil), double sided component