M48Z12-200PC1集成電路（IC）的存儲(chǔ)器規(guī)格書(shū)PDF中文資料

M48Z12-200PC1屬于集成電路（IC）的存儲(chǔ)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的M48Z12-200PC1存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性?xún)煞N，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線(xiàn)、SPI、UFS、Xccela 總線(xiàn)和 1-線(xiàn)。

Description

The M48Z02/12 ZEROPOWER? RAM is a 2 K x 8 non-volatile static RAM which is pin and function compatible with the DS1220.

A special 24-pin, 600 mil DIP CAPHAT? package houses the M48Z02/12 silicon with a long-life lithium button cell to form a highly integrated battery-backed memory solution.

The M48Z02/12 button cell has sufficient capacity and storage life to maintain data functionality for an accumulated time period of at least 10 years in the absence of power over commercial operating temperature range.

The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

Features

■ Integrated, ultra low power SRAM and power fail control circuit

■ Unlimited WRITE cycles

■ READ cycle time equals WRITE cycle time

■ Automatic power-fail chip deselect and WRITE protection

■ WRITE protect voltages

(VPFD = power-fail deselect voltage):

– M48Z02: VCC= 4.75 to 5.5 V;

4.5 V ≤ VPFD ≤ 4.75 V

– M48Z12: VCC= 4.5 to 5.5 V;

4.2 V ≤ VPFD ≤ 4.5 V

■ Self-contained battery in the CAPHAT? DIP package

■ Pin and function compatible with JEDEC standard 2 K x 8 SRAMs

■ RoHS compliant

– Lead-free second level interconnect