M48Z58Y-70PC6中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

Description

The M48Z58/Y ZEROPOWER? RAM is an 8 Kbit x 8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory solution.

Features

■ Integrated, ultra low power SRAM, power-fail control circuit, and battery

■ READ cycle time equals WRITE cycle time

■ Automatic power-fail chip deselect and WRITE protection

■ WRITE protect voltages: (VPFD = power-fail deselect voltage)

– M48Z58: VCC = 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V

– M48Z58Y: VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V

■ Self-contained battery in the CAPHAT? DIP package

■ Packaging includes a 28-lead SOIC and SNAPHAT? top (to be ordered separately)

■ SOIC package provides direct connection for a SNAPHAT? top which contains the battery

■ Pin and function compatible with JEDEC standard 8 Kbit x 8 SRAMs

■ RoHS compliant

– Lead-free second level interconnect