M5M410092BRF中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

Introduction

One of the traditional bottlenecks of 3D graphics hardware has been the rate at which pixels can be rendered into a frame buffer using conventional DRAM or VRAM. The 3D-RAM emerged from a complete rethinking of frame buffer technology and produces an order of magnitude increase in rendering performance.

The factors responsible for the dramatic overall performance improvement include:

? New Memory Architecture

? 10-Mbits DRAM array supporting 1280 x 1024 x 8 frame buffer

? Four independent, interleaved DRAM banks

? 2048-bit SRAM Pixel Buffer as the cache between DRAM and ALU

? Built-in tile-oriented memory addressing for rendering and scan line-oriented memory addressing for video refresh

? 256-bit global bus connecting DRAM banks and Pixel Buffer

? Flexible dual Video Buffer supporting 85-Hz CRT refresh

? Write Mostly Interface

? On-chip ALU

? Four ROP units supporting 16 raster operations on byte data

? Four Blend units blending the old pixel value with new information

? On-chip hardware acceleration for all OpenGL blending modes(NEW)

? On-chip hardware acceleration for all OpenGL stencil modes (NEW)

? One 32-bit Match Comparator and one 32-bit Magnitude Comparator

? Concurrent operations of DRAM, Pixel Buffer, ALU and Video Buffer

? 32-bit synchronous high-bandwidth data bus interface with rendering controller

? Blending operations in both (8, 8, 8, 8) and (4, 4, 4, 4) color modes (NEW)

? One additional PASS_IN pin for flexible bit plane organization