M74HC165M1R中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift register fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Features

■ High speed:

– tPD = 15 ns (typ.) at VCC = 6 V

■ Low power dissipation:

– ICC = 4 μA (max.) at TA = 25 °C

■ High noise immunity:

VNIH = VNIL = 28 VCC (Min.)

■ Symmetrical output impedance:

|IOH| = IOL = 4 mA (min)

■ Balanced propagation delays: tPLH ? tPHL

■ Wide operating voltage range:

VCC (opr) = 2 V to 6 V

■ Pin and function compatible with 74 series 165