M74HC643B1R中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The M54/74HC245, HC640 and HC643 utilise silicon gate C2MOS technology to achive operating speeds equivalent to LSTTL devices.

Along with the low power dissipation and high noise immunity of standards C2MOS integrated circuit, it possesses the capability to drive 15 LSTTL loads.

These IC’s are intended for two-way asynchronous communication between data buses, and the direction of data trasmission is determined by DIR input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.

All input are equipped with protection circuits against staticdischarge and transient discharge and transient excess voltage.

IT IS PROHIBITED TO APPLY A SIGNAL TO A BUS TERMINAL WHEN IT IS IN OUTPUT MODE AND WHEN A BUS THERMINAL IS FLOATING (HIGH IMPEDANCE STATE), IT IS REQUESTED TO FIX THE INPUT LEVEL BY MEANS OF EXTERNAL PULL DOWN OR PULL UP RESISTOR.

■ HIGH SPEED

tPD = 10 ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION

ICC = 4 μA (MAX.) at TA = 25 oC

■ HIGH NOISE IMMUNITY

VNIH = VINL = 28 VCC (MIN.)

■ OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS

■ SYMMETRICAL OUTPUT IMPEDANCE

|IOH| = IOL = 6 mA (MIN)

■ BALANCED PROPAGATION DELAYS tPLH = tPHL

■ WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS245/640/643