MB86606A中文資料富士通數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

■DESCRIPTION

The MB86606A is an intelligent SCSI protocol controller (SPC) conforming to the ANSI (FAST-20) standard and integrating a PCI local bus interface function. The specification of SCSI controller block is based on the MB86605’s one which is a Wide SCSI protocol controller, but the device functions/features to achieve the FAST-20 data transfer rate of maximum 40 Mbyte/sec at 16-bit FAST-20 SCSI, such as the size of internal data register FIFO, are larged on the MB86606A. As for the SCSI bus pins, a totem pole type single-ended driver/receiver is incorporated in the device so that it can drive the SCSI bus directly. Furthermore, the MB86606A is capable of connecting the external differential type driver/receiver.

■FEATURES

SCSI Protocol Controller Block:

? Operable as initiator and target

? WIDE and FAST-20 data transfers

Synchronous transfer (max. 40 Mbytes/s: Up to 256 offset values can be set.)

Asynchronous transfer (max. 10 Mbytes/s)

? 512-byte FIFO register for data phase

? Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases (MCS Buffers)

? On-chip totem pole type SCSI single-ended driver/receiver

? Supports external SCSI differential driver/receiver connectivity

? On-chip memory to store transfer parameters for each ID (up to 15 connected devices)

? On-chip 16-bit transfer block counter and 24-bit transfer byte counter

Maximum Transfer Byte : 1 Tbyte at fixed length data transfer : 16 Mbyte at variable length data transfer

? Supports various control commands:

Sequential Commands : can perform phase-to-phase sequential operations (functions only when issuing from a system side.)

Discrete Commands : can perform any desired sequence to program in the user program memory

Data Transfer Commands : can program the transfer data length at the user program operation.

? On-chip direct control register for SCAM (SCSI Configured AutoMatically) Level-1 Protocol

? Supports Multi Selection/Reselection Responses

Selection and Reselection responses can be done to plural IDs.

? On-chip 2 Kbyte User Program Memory

Two Modes : 2 Kbyte ×1 bank and 1 Kbyte ×2 banks

(While 1 Kbyte ×2 banks are selected, host system can access another bank even if the user

program is executing.)

Access to User program : Burst transfer via I/O access port

: Direct access to 2 Kbyte user program memory (only for PCI bus I/F mode)

? User Selectable Interrupt Report

Unnecessary interrupt reports can be disabled depending on user’s applications to reduce a system ISR

overhead.

? Two automatic receive modes

Initiator : can automatically receive information for new phase to which target switched

Target : can automatically receive attention condition generated by initiator

? Automatic selection/reselection

For command issues : automatically performs to receive MSG/CMD to the selection/reselection

request from partner device

For user program operation : pauses the program currently executed and automatically jumps to the

specified selection /reselection routine in response to the selection/reselection

request from partner device.

? Operation Clock

System Clock: Max. 40 MHz

Internal Processor Operating Clock: Max. 20 MHz