MC10E196集成電路（IC）的延遲線規(guī)格書(shū)PDF中文資料

MC10E196屬于集成電路（IC）的延遲線。由安森美半導(dǎo)體公司制造生產(chǎn)的MC10E196延遲線時(shí)鐘延遲線產(chǎn)品族中的產(chǎn)品屬于數(shù)字器件，用于在數(shù)字信號(hào)中引入時(shí)間延遲，以便將提交給器件輸入的信號(hào)躍遷，經(jīng)過(guò)某一已知時(shí)間之后在輸出端復(fù)現(xiàn)。它們常用于高速數(shù)字系統(tǒng)，以校正或補(bǔ)償不同信號(hào)路徑之間的信號(hào)傳播時(shí)間的偏差。這些器件可用于產(chǎn)生固定、可選或可變持續(xù)時(shí)間的延遲。

Description

The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications.

The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps.

These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control.

The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps Least Significant Bit (LSB) minimum resolution still further. The FTUNE input is what differentiates the E196 from the E195.

An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 μF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

? 2.0 ns Worst Case Delay Range

? ≈20 ps/Delay Step Resolution

? Linear Input for Tighter Resolution

? >1.0 GHz Bandwidth

? On Chip Cascade Circuitry

? PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

? NECL Mode Operating Range: VCC = 0 V with VEE = ?4.2 V to ?5.7 V

? Internal Input 50 kΩ Pulldown Resistors

? ESD Protection:

Human Body Model; > 1 kV,

Machine Model; > 75 V

? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

? Moisture Sensitivity Level: Pb = 1; Pb?Free = 3

For Additional Information, see Application Note AND8003/D

? Flammability Rating: UL 94 V?0 @ 1.125 in, Oxygen Index: 28 to 34

? Transistor Count = 425 devices

? Pb?Free Packages are Available*