MC14490DWR2集成電路（IC）的專用邏輯器件規(guī)格書PDF中文資料

MC14490DWR2屬于集成電路（IC）的專用邏輯器件。由安森美半導(dǎo)體公司制造生產(chǎn)的MC14490DWR2專用邏輯器件專用邏輯 IC 設(shè)計(jì)提供應(yīng)用特定的邏輯輸出類型，例如 BCD 速率倍增、可尋址掃描端口、總線終端陣列、CML 驅(qū)動(dòng)器、比較器、ABT 掃描測(cè)試、二進(jìn)制全加法器、互補(bǔ)對(duì)加逆變器、可配置緩沖器、觸點(diǎn)顫動(dòng)消除器、晶體振蕩器、延遲元件、差分接收器、LVTTL 到 GTLP 收發(fā)器、存儲(chǔ)器解碼器、電源良好檢測(cè)器和分頻器。

The MC14490 is constructed with complementary MOS enhancement mode devices, and is used for the elimination of extraneous level changes that result when interfacing with mechanical contacts. The digital contact bounce eliminator circuit takes an input signal from a bouncing contact and generates a clean digital signal four clock periods after the input has stabilized. The bounce eliminator circuit will remove bounce on both the “make” and the “break” of a contact closure. The clock for operation of the MC14490 is derived from an internal R–C oscillator which requires only an external capacitor to adjust for the desired operating frequency (bounce delay). The clock may also be driven from an external clock source or the oscillator of another MC14490 (see Figure 5).

? Diode Protection on All Inputs

? Six Debouncers Per Package

? Internal Pullups on All Data Inputs

? Can Be Used as a Digital Integrator, System Synchronizer, or Delay

Line

? Internal Oscillator (R–C), or External Clock Source

? TTL Compatible Data Inputs/Outputs

? Single Line Input, Debounces Both “Make” and “Break” Contacts

? Does Not Require “Form C” (Single Pole Double Throw) Input

Signal

? Cascadable for Longer Time Delays

? Schmitt Trigger on Clock Input (Pin 7)

? Supply Voltage Range = 3.0 V to 18 V

? Chip Complexity: 546 FETs or 136.5 Equivalent Gates