MGT5100TS中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

Features

603e series processor core that implements the PowerPC architecture

? Superscalar architecture

? 0 – 231MHz static operation (extended temperature range)

? 16K Instruction/16K Data Caches

? Double precision FPU

? Instruction and Data MMU

? Dynamic power management including Doze and Sleep modes

? True little endian and big endian support

? Standard & critical interrupt capability

High speed SDRAM memory interface

? 66MHz operation

? SDRAM & DDR SRAM support

? 128Mbyte addressing range

? 32-bit data bus

? Built-in initialization and refresh

Flexible multi-function external bus

? Supports PCI, ATA/IDE, and ROM/RAM/Flash interfaces

? Version 2.2 PCI master compatibility

– 32-bit muxed address/data

– 33MHz operation with SmartComm‘ enabled

? Version 4 ATA compatible external interface

– IDE Disk Drive connectivity

? ROM/RAM/Flash interface

– Boot ROM, external peripheral connectivity

SmartComm I/O subsystem

? SmartComm virtual DMA controller

? Dedicated DMA channels for reception and transmission for all peripheral

interfaces

? Programmable Serial Controllers (PSCx)

– UART or RS232 interface

– CODEC interface for modem or AC97 audio

– Bluetooth, cellular, GPS, digital radio interface

? 10/100 BaseT Ethernet

? USB Master 1.1 with OHCI support

– Support for two independent USB ports

? Infrared (IR) data port

– Two IR receive ports (Standard IR & IrDA)

– IRBlaster

– IrDA 1.0 SIR mode to 115.2kbps

– IrDA 1.1 MIR and FIR modes to 4.0Mbps

? I2C Controller(s) to 520Kbps

– Support for two independent I2C ports

? Serial Peripheral Interface (SPI) controller

Dual MSCAN 2.0 A/B Controller modules

? Motorola Scalable Controller Area Network (MSCAN) architecture

? V2.0 A/B CAN protocol

? Standard and extended data frames

? Programmable bit rate up to 1Mbps (High Speed or Low Speed)

System level features

? Six programmable chip selects

? Interrupt controller

– Four external interrupt request lines supporting standard and/or critical

interrupts

– Support for all other internal interrupt sources

? GPIO / Timer functions

– Two dedicated GPIO pins supporting WakeUp capability

– Eight dedicated GPIO pins with timer capability supporting input capture,

output compare, and Pulse Width Modulation (PWM) functions

– Up to 56 total GPIO pins (depending on functional muxing selections)

? Systems Protection (watch dog timer, bus monitor)

? Real-time clock

? Power management features

Test / Debug features

? JTAG (IEEE 1149.1 test access port)

? Common On-Chip Processor (COP) debug port

On-board PLL and clock generation

Software Development Support

? Complete software development tool chain

? Optional accessory development kits

? Robust silicon evaluation kits

? Technical support

? Professional services