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MH64D72KLH-75中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

MH64D72KLH-75
廠商型號

MH64D72KLH-75

功能描述

4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

文件大小

350.07 Kbytes

頁面數(shù)量

39

生產(chǎn)廠商 Mitsubishi Electric Semiconductor
企業(yè)簡稱

Mitsubishi三菱電機

中文名稱

三菱電機株式會社官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-2-22 18:00:00

人工找貨

MH64D72KLH-75價格和庫存,歡迎聯(lián)系客服免費人工找貨

MH64D72KLH-75規(guī)格書詳情

DESCRIPTION

The MH64D72KLH is 67108864 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

This consists of 18 industry standard 32M x 8 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.

This socket-ty pe memory module is suitable f or main memory in computer systems and easy to interchange or add modules.

FEATURES

- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package.

- Vdd=Vddq=2.5v ±0.2V

- Double data rate architecture; two data transf ers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data

- Dif f erential clock inputs (CK0 and /CK0)

- data and data mask ref erenced to both edges of DQS

- /CAS latency - 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Auto precharge / All bank precharge controlled by A10

- 8192 ref resh cycles /64ms

- Auto ref resh and Self ref resh

- Row address A0-12 / Column address A0-9

- SSTL_2 Interf ace

- Module 2bank Conf igration

- Burst Ty pe - sequential/interleav e(programmable)

- Commands entered on each positiv e CLK edge

APPLICATION

Main memoryunit for PC, PC server, Server, W S.

產(chǎn)品屬性

  • 型號:

    MH64D72KLH-75

  • 制造商:

    MITSUBISHI

  • 制造商全稱:

    Mitsubishi Electric Semiconductor

  • 功能描述:

    4,831,838,208-BIT(67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

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