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MK2049-35SI中文資料ICST數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
MK2049-35SI |
| 功能描述 | 3.3 V Communications Clock PLL |
| 文件大小 |
125.68 Kbytes |
| 頁面數(shù)量 |
10 頁 |
| 生產(chǎn)廠商 | Integrated Circuit Systems |
| 企業(yè)簡(jiǎn)稱 |
ICST |
| 中文名稱 | Integrated Circuit Systems官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-5-3 16:00:00 |
| 人工找貨 | MK2049-35SI價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
MK2049-35SI規(guī)格書詳情
Description
The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems.
Features
? Packaged in 20 pin SOIC
? 3.3 V ±5 operation
? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
? Locks to 8 kHz ±100 ppm (External mode)
? Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.5 or x1/x2 outputs
? Exact internal ratios enable zero ppm error
? Output clock rates include T1, E1, T3, E3, and OC3 submultiples
? See the MK2049-01, -02, and -03 for more selections at VDD = 5 V, and the MK2049-34 for more selections at 3.3 V
產(chǎn)品屬性
- 型號(hào)：
MK2049-35SI
- 制造商：
Integrated Device Technology Inc
- 功能描述：
49.152 MHz, OTHER CLOCK GENERATOR, PDSO20
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
24+ |
5000 |
公司存貨 |
詢價(jià) | ||||
ICS |
1535+ |
559 |
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24+ |
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28500 |
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3000 |
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DIODES |
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DFN |
3761 |
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2447 |
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100500 |
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13 |
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SOP20-7.2 |
12800 |
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詢價(jià) |
