MK68564Q-04中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The MK68564 SIO (Serial Input Output) is a dualchannel, multi-function peripheral circuit, designed to satisfy a wide variety of serial data communications requirements in microcomputer systems. Its basicfunction is a serial-to-parallel, parallel-to-serial converter/controller ; however within that role, it is systems software configurable so that its ”personality” may be optimized for any given serial data communications application.

■ COMPATIBLE WITH MK68000 CPU

■ COMPATIBLE WITH MK68000 SERIES DMA’s

■ TWO INDEPENDENT FULL-DUPLEX CHANNELS

■ TWO INDEPENDENT BAUD-RATE GENERATORS

- Crystal oscillator input

- Single-phase TTL clock input

■ DIRECTLY ADDRESSABLE REGISTERS (all control registers are read/write)

■ DATA RATE IN SYNCHRONOUS OR ASYNCHRONOUS MODES

- 0-1.25M bits/second with 5.0MHz system clock rate

■ SELF-TEST CAPABILITY

■ RECEIVE DATA REGISTERS ARE QUADRUPLY BUFFERED ; TRANSMIT REGISTERS ARE DOUBLY BUFFERED

■ DAISY-CHAIN PRIORITY INTERRUPT LOGIC PROVIDES AUTOMATIC INTERRUPT VECTORING WITHOUT EXTERNAL LOGIC

■ MODEM STATUS CAN BE MONITORED

- Separate modem controls for each channel

■ ASYNCHRONOUS FEATURES

- 5, 6, 7, or 8 bits/character

- 1, 11/2, or 2 stop bits

- Even, odd, or no parity

- x1, x16, x32, and x64 clock modes

- Break generation and detection

- Parity, overrun, and framing error detection

■ BYTE SYNCHRONOUS FEATURES

- Internal or external character synchronization

- One or two sync characters in separate registers

- Automatic sync character insertion

- CDC-16 or CRC-CCITT block check generation and checking

■ BIT SYNCHRONOUS FEATURES

- Abort sequence generation and detection

- Automatic zero insertion and deletion

- Automatic flag insertion between messages

- Address field recognition

- I-field residue handling

- Valid receive messages protected from overrun

- CRC-16 or CRC-CCITT block check generation and checking