MPC9100中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

Dual PLL Clock Generator

The MPC9100 is a dual PLL phase locked loop clock generator. The device synthesizes a 14.318 MHz input reference to provide a buffered copy of the input reference, a 31.3344MHz clock output and a 45.1584 clock output.

The device features a fully integrated crystal oscillator as the clock reference source. No external components are required other than the 14.318 MHz crystal. The TCLK input is used only for factory test and cannot be used as the PLL clock reference. To reduce total die area the PLL loop filter capacitors are brought outside the chip. The FCAP pins are used to connect these capacitors to the internal PLL’s. 0.01μf capacitors are recommended.