MSC7119VF1200集成電路（IC）的DSP（數(shù)字信號(hào)處理器）規(guī)格書(shū)PDF中文資料

Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

? StarCore? SC1400 DSP extended core with one SC1400 DSP

core, 256 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte

instruction cache (ICache), four-entry write buffer, programmable

interrupt controller (PIC), and low-power Wait and Stop

processing modes.

? 192 Kbyte M2 memory for critical data and temporary data

buffering.

? 8 Kbyte boot ROM.

? AHB-Lite crossbar switch that allows parallel data transfers

between four master ports and six slave ports, where each port

connects to an AHB-Lite bus; fixed or round robin priority

programmable at each slave port; programmable bus parking at

each slave port; low power mode.

? Internal PLL generates up to 300 MHz clock for the SC1400 core

and up to 150 MHz for the crossbar switch, DMA channels, M2

memory, and other peripherals.

? Clock synthesis module provides predivision of PLL input clock;

independent clocking of the internal timers and DDR module;

programmable operation in the SC1400 low power Stop mode;

independent shutdown of different regions of the device.

? Enhanced 16-bit wide host interface (HDI16) provides a glueless

connection to industry-standard microcomputers,

microprocessors, and DSPs and can also operate with an 8-bit host

data bus, making if fully compatible with the DSP56300 HI08

from the external host side.

? DDR memory controller that supports byte enables for up to a

32-bit data bus; glueless interface to 150 MHz 14-bit page mode

DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;

and 16-bit or 32-bit external data bus.

? Programmable memory interface with independent read buffers,

programmable predictive read feature for each buffer, and a write

buffer. (Continue ...)