MT28S2M32B1LC中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERAL DESCRIPTION

This 64Mb SyncFlash? data sheet is divided into two major sections. The SDRAM Interface Functional Description details compatibility with the SDRAM memory, and the Flash Memory Functional Description specifies the symmetrical-sectored Flash architecture and functional commands.

FEATURES

? PC133 SDRAM-compatible read timing

? Fully synchronous; all signals registered on positive edge of system clock

? Internal pipelined operation; column address can be changed every clock cycle

? Internal banks for hiding row access

? Programmable burst lengths: 1, 2 , 4, 8, or full page (read) 1, 2, 4, or 8 (write)

? LVTTL-compatible inputs and outputs

? Single 3.0V–3.6V power supply Additional VHH hardware protect mode (RP#)

? Supports CAS latency of 1, 2, and 3

? Four-bank architecture supports true concurrent operation with zero latency Read any bank while programming or erasing any other bank

? Deep power-down mode: 50μA (MAX)

? Cross-compatible Flash memory command set