MT46V64M4TG-75Z中文資料鎂光數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The DDR333 SDRAM is a high-speed CMOS, dy namic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture.

FEATURES

? 167 MHz Clock, 333 Mb/s/p data rate

?VDD= +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

? Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)

? Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

? Differential clock inputs (CK and CK#)

? Commands entered on each positive CK edge

? DQS edge-aligned with data for READs; center aligned with data for WRITEs

? DLL to align DQ and DQS transitions with CK

? Four internal banks for concurrent operation

? Data mask (DM) for masking write data (x16 has two - one per byte)

? Programmable burst lengths: 2, 4, or 8

? Concurrent Auto Precharge option supported

? Auto Refresh and Self Refresh Modes

? FBGA package available

? 2.5V I/O (SSTL_2 compatible)

? tRAS lockout (tRAP =tRCD)

? Backwards compatible with DDR200 and DDR266