N74F524D中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The 74F524 is an 8-bit bidirectional register with parallel input and output, plus serial input and output progressing from MSB to LSB. All data inputs, serial and parallel, are loaded by the rising edge of the clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-High, open collector outputs representing ‘register equal to bus’, ‘register greater than bus’ and ‘register less than bus’ are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow Two’s Complement as well as magnitude compare. Linking inputs are provided for expansion to longer words.

FEATURES

? 8-Bit bidirectional register with bus-oriented input-output

? Independent serial input-output to register

? Register bus comparator with ‘equal to’, ‘greater than’ and ‘less than’ outputs

? Cascadable in groups of 8-bits

? Open collector comparator outputs for AND-wired expansion

? Two’s complement or magnitude compare