ORT82G5集成電路（IC）的FPGA（現(xiàn)場可編程門陣列）規(guī)格書PDF中文資料

Introduction

Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively. Each channel operates at up to 3.7 Gbps across 26 inches of FR-4 backplane, with a full-duplex synchronous interface with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K usable FPGA system gates. The CDR circuitry available from Lattice’s high-speed I/O portfolio (sysHSI?), has already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet (GbE, 10 GbE) applications.