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P102-04SC中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書

P102-04SC
廠商型號

P102-04SC

功能描述

Low Skew Output Buffer

文件大小

236.44 Kbytes

頁面數(shù)量

6

生產(chǎn)廠商 PhaseLink Corporation
企業(yè)簡稱

PLL

中文名稱

PhaseLink Corporation官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2025-2-7 17:48:00

P102-04SC規(guī)格書詳情

DESCRIPTION

The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.

FEATURES

? Frequency range 50 ~ 120MHz.

? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).

? Zero input - output delay.

? Less than 700 ps device - device skew.

? Less than 250 ps skew between outputs.

? Less than 200 ps cycle - cycle jitter.

? Output Enable function tri-state outputs.

? 3.3V operation.

? Available in 8-Pin 150mil SOIC.

產(chǎn)品屬性

  • 型號:

    P102-04SC

  • 制造商:

    PLL

  • 制造商全稱:

    PLL

  • 功能描述:

    Low Skew Output Buffer

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