PCA9527DP集成電路（IC）的信號緩沖器、中繼器、分離器規(guī)格書PDF中文資料

General description

The PCA9527 is a 3-channel bidirectional open-drain bus buffer for Display Data Control (DDC) clock, data and Consumer Electronic Control (CEC) for HDMI application. The device has two power supply pins to allow voltage level shift from 2.7 V to 5 V, and a rise time accelerator on port A of each DDC clock and data for driving longer cable (up to 18 meters or 1400 pF reliably without violating the bus rise time). The 5 V tolerant CEC channel is internally connected to VCC(B) and has no rise time accelerator. The CEC channel can be used as an interrupt or reset.

Features

■ 3-channel, bidirectional buffer isolates capacitance allowing 1400 pF on port A and 400 pF on port B

■ Exceeds 18 meters (above the maximum distance for HDMI DDC)

■ Rise time accelerator and normal I/O on port A (no accelerator for CEC)

■ Static level offset on port B

■ Voltage level translation from 2.7 V to 5.5 V

■ CEC is 5 V tolerant, powered by VCC(B)

■ Upgrade replacement over PCA9507 and PCA9517A for cable application

■ I2C-bus, SMBus and DDC-bus compatible

■ Active HIGH buffer enable input

■ Open-drain input/outputs

■ Lock-up free operation

■ Supports arbitration and clock stretching across the repeater

■ Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters

■ Powered-off high-impedance I2C-bus pins

■ Port A operating supply voltage range of 2.7 V to 5.5 V

■ Port B operating supply voltage range of 2.7 V to 3.6 V

■ 5 V tolerant I2C-bus and enable pins

■ 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater)

■ ESD protection exceeds 8000 V HBM per JESD22-A114, 500 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Package offered: TSSOP10