PCK953BDSLASHG中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

General description

The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.

Features

■ Fully integrated PLL

■ Output frequency up to 125 MHz in PLL mode

■ Outputs disable in high-impedance

■ LQFP32 packaging

■ 55 ps cycle-to-cycle jitter typical

■ 9 mA quiescent current typical

■ 60 ps static phase offset typical