PEF20550中文資料英飛凌數(shù)據(jù)手冊PDF規(guī)格書

Overview

The PEB 20550 (Extended Line Card Controller) is a highly integrated controller circuit optimized for line card and key system applications. It combines all functional blocks necessary to manage up to 32 digital (ISDN or proprietary) or 64 analog subscribers.

The switching and layer-1 control capability of the EPIC-1 (PEB 2055) constitutes a major functional block of the ELIC.

Features

Switching (EPIC?-1)

? Non-blocking switch for 32 digital (e.g. ISDN) or 64 voice subscribers

– Bandwidth 16, 32, or 64 kbit/s

– Two consecutive 64-bit/s channels can be switched as a single 128-kbit/s channel

? Freely programmable time slot assignment for all subscribers

? Synchronous μP-access to two selected channels

? Two types of serial interfaces independently programmable over a wide data range (128 - 8192 kbit/s)

– PCM-interface

Tristate control signals for external drivers

Programmable clock shift

Single or double data clock

– Configurable interface

Configurable for IOM-, SLD- and PCM-applications

High degree of flexibility for datastream adaption

Programmable clockshift

Single or double data clock

Handling of Layer-1 Functions (EPIC?-1)

? Change detection for C/I-channel (IOM-configuration) or feature control (SLD-configuration)

? Additional last-look logic for feature control (SLD-configuration)

? Buffered monitor (IOM-configuration) or signaling channel (SLD-configuration)

Handling of Layer-2 Functions (SACCO)

? Two independent full duplex HDLC-channels

– Serial interface

Data rate up to 4 Mbit/s

Independent time slot assignment for each channel with programmable time slot

length (1-256 bits)

Support of bus configuration with collision resolution

Continuous transmission of 1 to 32 bytes possible

– Protocol support

Auto-mode, fully compatible to PEB 2050 (PBC) protocol

Non-auto mode, address recognition capability

Transparent mode, HDLC-framing only

Extended transparent mode, fully transparent without HDLC-framing

– 64-bytes FIFO’s per HDLC-channel and direction

D-channel Multiplexing (D-channel arbiter)

? Serving of multiple subscribers with one HDLC-controller

? Full duplex signaling protocols (e.g. LAPD or proprietary) supported

? Programmable priority scheme

? Broadcast transmission

Line Card Glue Logic

? Power-up reset generator

? Watchdog timer

? Parallel ports (8-bit input, 4-bit I/O)

Boundary Scan Support

? Fully IEEE 1149.1 compatible

? 32-bit device identification register

Bus Interface

? Siemens/Intel or Motorola type μP-interface

? 8-bit demultiplexed bus interface

? FIFO-access interrupt or DMA controlled