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PEF2256HV2.2中文資料英飛凌數(shù)據(jù)手冊PDF規(guī)格書

PEF2256HV2.2
廠商型號

PEF2256HV2.2

功能描述

E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

文件大小

6.1164 Mbytes

頁面數(shù)量

518

生產(chǎn)廠商 Infineon Technologies AG
企業(yè)簡稱

Infineon英飛凌

中文名稱

英飛凌科技股份公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-2-12 10:06:00

PEF2256HV2.2規(guī)格書詳情

Introduction

The FALC?56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems.

Features

Line Interface

? High-density, generic interface for all E1/T1/J1 applications

? Analog receive and transmit circuits for long-haul and short-haul applications

? E1 or T1/J1 mode selectable

? Data and clock recovery using an integrated digital phase-locked loop

? Maximum line attenuation up to -43 dB at 1024 kHz (E1) and up to -36 dB at 772 kHz (T1/J1)

? Programmable receive equalizer characteristic

? Software-selectable receive line termination

? Programmable transmit pulse shapes for E1 and T1/J1 pulse masks

? Programmable line build-out for CSU signals according to ANSI T1. 403 and FCC68: 0dB, -7.5 dB, -15 dB, -22.5 dB (T1/J1)

? Low transmitter output impedances for high transmit return loss

? Tristate function of the analog transmit line outputs

? Analog switch for redundancy applications

? Transmit line monitor protecting the device from damage

? Receive line monitor mode

? Jitter specifications of ITU-T I.431, G.703, G.736 (E1), G.823 (E1) and AT&T TR62411 (T1/J1) are met

? Crystal-less wander and jitter attenuation/compensation

? Common master clock reference for E1 and T1/J1 (any frequency within 1.02 and 20 MHz)

? Power-down function

? Support of automatic protection switching

? Dual-rail or single-rail digital inputs and outputs

? Unipolar NRZ or CMI for interfacing fiber-optical transmission routes

? Selectable line codes (E1: HDB3, AMI/T1: B8ZS, AMI with ZCS)

? Loss-of-signal indication with programmable thresholds according to ITU-T G.775, ETS300233 (E1) and ANSI T1.403 (T1/J1)

? Optional data stream muting upon LOS detection

? Programmable receive slicer threshold

? Clock generator for jitter-free system/transmit clocks per channel

? Local loop and remote loop for diagnostic purposes

? Low power device

? Single power supply (3.3 V) or dual power supply (3.3 V and 1.8 V)

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產(chǎn)品屬性

  • 型號:

    PEF2256HV2.2

  • 功能描述:

    網(wǎng)絡(luò)控制器與處理器 IC T/E

  • RoHS:

  • 制造商:

    Micrel

  • 產(chǎn)品:

    Controller Area Network(CAN)

  • 電源電流(最大值):

    595 mA

  • 最大工作溫度:

    + 85 C

  • 安裝風(fēng)格:

    SMD/SMT

  • 封裝/箱體:

    PBGA-400

  • 封裝:

    Tray

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