首頁(yè)>PLL102-109XI>規(guī)格書詳情
PLL102-109XI中文資料PLL數(shù)據(jù)手冊(cè)PDF規(guī)格書
PLL102-109XI規(guī)格書詳情
DESCRIPTIONS
The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVDD to ground.
FEATURES
? PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
? Distributes one clock Input to one bank of six differential outputs.
? Track spread spectrum clocking for EMI reduction.
? Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled.
? Two independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ±100ps.
? Support 2-wire I2C serial bus interface.
? 2.5V Operating Voltage.
? Available in 28-Pin 209mil SSOP.
產(chǎn)品屬性
- 型號(hào)：
PLL102-109XI
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Programmable DDR Zero Delay Clock Driver
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
PHASELIN |
23+ |
NA/ |
30 |
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價(jià) | ||
PHASELIN |
SSOP48 |
899933 |
集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢價(jià) | |||
24+ |
SSOP |
2700 |
全新原裝自家現(xiàn)貨優(yōu)勢(shì)! |
詢價(jià) | |||
PHASELIN |
22+ |
SSOP48 |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價(jià) | ||
PHASELIN |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量 |
詢價(jià) | ||||
PHASELIN |
0350+ |
SSOP48 |
30 |
普通 |
詢價(jià) | ||
PHASELINK |
23+ |
SSOP |
89630 |
當(dāng)天發(fā)貨全新原裝現(xiàn)貨 |
詢價(jià) | ||
24+ |
SSOP |
17 |
詢價(jià) | ||||
PHASELIN |
23+ |
SSOP48 |
2530 |
原廠原裝正品 |
詢價(jià) | ||
PHASELINK |
22+23+ |
SSOP |
36452 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) |
